1. Field of the Disclosure
Generally, the present disclosure relates to sophisticated integrated circuits, and, more particularly, to the fabrication of an RRAM cell with, in one embodiment, one or more bottom electrodes formed by silicidation using CMOS compatible processes.
2. Description of the Related Art
Memory circuits and devices are widely used in the electronics industry. In general, memory devices permit the storage of a “bit” of information, i.e., a “1” (logically high) or a “0” (logically low) signal. Vast numbers of these memory devices are formed on a single chip so as to permit the storage of a vast quantity of digital information. Various forms of such devices, and read/write circuitry employed with such devices, have been used in the industry for years, e.g., RAM (Random Access Memory) devices, ROM (Read Only Memory) devices, EEPROM (Electrically Erasable Read Only Memory) devices, etc.
Nonvolatile memory is a type of memory that retains stored data when power is removed from the memory device. Such nonvolatile memory devices are widely employed in mobile communication devices, computers, memory cards, etc. Flash memory is an example of one type of nonvolatile memory that is greatly used in such modern electronic devices.
More recently, another form of memory, RRAM (Resistance Random Access Memory) has been introduced to the industry. FIGS. 1A-1B schematically depict an illustrative prior art RRAM device 100. Basically, such a prior art RRAM device 100 is comprised of a multilayered stack of materials, and it is fabricated using a layer-by-layer technique. As shown in FIG. 1A, in one embodiment, the prior art RRAM device 100 comprises a top electrode 102, a tunnel oxide 104, a layer of conductive metal oxide 106, and a bottom electrode 108. The top electrode 102 and the bottom electrode 108 may be comprised of, for example, platinum. The tunnel oxide layer 104 may be comprised of silicon dioxide and it may have an illustrative thickness of 20-50 Å. The conductive metal oxide layer 106 may be comprised of TiO2 or Cr-doped SrTiO3.
FIG. 1B schematically depicts how the RRAM device 100 works. In the depicted example, a positive voltage V+ is applied to the top electrode 102, while the bottom electrode 108 is coupled to ground (“GRND”). Application of the positive voltage V+ attracts negatively charged ions 110 from the conductive metal oxide layer 106 which thereby causes breakdown of the tunnel oxide 104. This breakdown results in the establishment of an electrical current path between the top electrode 102 and the bottom electrode 108, and the resulting electrical current can be measured. Application of a negative voltage (V−) to the top electrode 102 forces or repels the negatively charged ions 110 back toward the conductive metal oxide layer 106. This action “turns off” the conductive current path that was previously established, and cuts off the previously established current flow.
Importantly, as noted above, the prior art RRAM device 100 is made using a traditional layer-by-layer approach that involves many discrete deposition, lithography and etching steps, perhaps for each layer of the device. Such a layered construction of the prior art RRAM device 100 makes it more difficult to incorporate it into integrated circuit devices that are manufactured using modern CMOS processing technology and methods. For example, fabrication of an RRAM device using the layer-by-layer approach may result in the overall height of the RRAM device 100 being greater than the height of other structures that are formed in traditional CMOS-type devices, such as PMOS and NMOS transistors. Such height differences can lead to patterning errors in photolithography operations and/or mandate additional processing steps be taken to avoid or reduce the adverse effects of such height differences, e.g., the performance of one or more additional deposition and planarization processes.
The present disclosure relates to methods and devices for avoiding or at least reducing the effects of one or more of the problems identified above.